1. Technical Field
This disclosure relates generally to memory systems, components, and methods and more particularly to a method and apparatus for providing debug functionality in a fully buffered memory channel that has no direct connection between an edge connector on a DIMM and the dynamic random access memory (DRAM) devices that reside on the DIMM.
2. Description of the Related Art
FIG. 1 is a block diagram illustrating a conventional memory channel 100 that exhibits a “stub bus” topology. The memory channel includes a host 110 and four DIMMs 120-150. Each of the DIMMs 120-150 is connected to the memory bus 115 to exchange data with the host 110. Each of the DIMMs 120-150 adds a short electrical stub to the memory bus 115. For approximately the past 15 years, memory subsystems have relied on this type of stub bus topology.
Simulations have shown that for applications of 2 to 4 DIMMs per memory channel, the stub bus technology reaches a maximum bandwidth of 533-667 MT/s (mega-transactions/second), or 4.2-5.3 GB/s (gigabytes/second) for an eight byte wide DIMM. Achieving the next significant level, 800 megatransfers/second (MT/s) and beyond, will be difficult if not impossible with the stub bus topology.